Preface to the Third Edition ix

Preface to the Second Edition xi

Preface xiii

1 Digital Systems and VLSI 1

           1.1  Why Design Integrated Circuits?  1

           1.2 Integrated Circuit Manufacturing 4

                        1.2.1 Technology 4

                        1.2.2 Economics 6

           1.3 CMOS Technology 15

                        1.3.1 CMOS Circuit Techniques 15

                        1.3.2 Power Consumption 16

                        1.3.3 Design and Testability 17

           1.4 Integrated Circuit Design Techniques 18

                        1.4.1 Hierarchical Design 19

                        1.4.2 Design Abstraction 22

                        1.4.3 Computer-Aided Design 28

           1.5  A Look into the Future 30

           1.6 Summary  31

           1.7  References  31

           1.8  Problems  32

2 Transistors and Layout 33

           2.1  Introduction  33

           2.2 Fabrication Processes  34

                        2.2.1 Overview 34

                        2.2.2 Fabrication Steps 37

           2.3  Transistors 40

                        2.3.1 Structure of the Transistor 40

                        2.3.2 A Simple Transistor Model 45

                        2.3.3 Transistor Parasitics 48

                        2.3.4 Tub Ties and Latchup 50

                        2.3.5 Advanced Transistor Characteristics 53

                        2.3.6 Leakage and Subthreshold Currents 60

                        2.3.7 Advanced Transistor Structures 61

                        2.3.8 Spice Models 61

           2.4 Wires and Vias  62

                        2.4.1 Wire Parasitics 65

                        2.4.2 Skin Effect in Copper Interconnect 72

           2.5  Design Rules 74

                        2.5.1 Fabrication Errors 75

                        2.5.2 Scalable Design Rules 77

                        2.5.3 SCMOS Design Rules 79

                        2.5.4 Typical Process Parameters 83

           2.6 Layout Design and Tools  83

                        2.6.1 Layouts for Circuits 83

                        2.6.2 Stick Diagrams 88

                        2.6.3 Layout Design and Analysis Tools 90

                        2.6.4 Automatic Layout 94

           2.7  References 97

           2.8  Problems 97

3 Logic Gates 105

           3.1  Introduction 105

           3.2  Static Complementary Gates 106

                        3.2.1 Gate Structures 106

                        3.2.2 Basic Gate Layouts 110

                        3.2.3 Logic Levels 113

                        3.2.4 Delay and Transition Time 118

                        3.2.5 Power Consumption 127

                        3.2.6 The Speed-Power Product 130

                        3.2.7 Layout and Parasitics 131

                        3.2.8 Driving Large Loads 134

           3.3 Switch Logic 135

           3.4  Alternative Gate Circuits 136

                        3.4.1 Pseudo-nMOS Logic 137

                        3.4.2 DCVS Logic 139

                        3.4.3 Domino Logic 141

           3.5 Low-Power Gates 146

           3.6  Delay Through Resistive Interconnect 152

                         3.6.1 Delay Through an RC Transmission Line 152

                         3.6.2 Delay Through RC Trees 155

                         3.6.3 Buffer Insertion in RC Transmission Lines 159

                         3.6.4 Crosstalk Between RC Wires  161

           3.7 Delay Through Inductive Interconnect 164

                         3.7.1 RLC Basics 165

                         3.7.2 RLC Transmission Line Delay 166

                         3.7.3 Buffer Insertion in RLC Transmission Lines  167

           3.8 References 169

           3.9 Problems  171

4 Combinational Logic Networks 177

           4.1  Introduction  177

           4.2 Standard Cell-Based Layout  178

                        4.2.1 Single-Row Layout Design 179

                        4.2.2 Standard Cell Layout Design 188