ContentsPreface . viFeatures . viiOnline Supplements viiiHow to Use the Software Tools in a Course ixLabs ixBugs xAcknowledgments xiChapter 1 From Zero to One 31.1 TheGamePlan 31.2 The Art of Managing Complexity . 41.2.1 Abstraction 41.2.2 Discipline 51.2.3 The Three-Y’s 61.3 The Digital Abstraction 71.4 Number Systems. 91.4.1 Decimal Numbers 91.4.2 Binary Numbers 91.4.3 Hexadecimal Numbers . 111.4.4 Bytes, Nibbles, and All That Jazz . 131.4.5 Binary Addition . 141.4.6 Signed Binary Numbers 151.5 Logic Gates 191.5.1 NOT Gate 201.5.2 Buffer 201.5.3 AND Gate 201.5.4 OR Gate . 211.5.5 Other Two-Input Gates 211.5.6 Multiple-Input Gates . 211.6 Beneath the Digital Abstraction 221.6.1 Supply Voltage 221.6.2 Logic Levels 221.6.3 Noise Margins 231.6.4 DC Transfer Characteristics 241.6.5 The Static Discipline . 241.7 CMOSTransistors 261.7.1 Semiconductors 271.7.2 Diodes 271.7.3 Capacitors 281.7.4 nMOS and pMOS Transistors 281.7.5 CMOS NOT Gate . 311.7.6 Other CMOS Logic Gates . 311.7.7 Transmission Gates 331.7.8 Pseudo-nMOS Logic . 331.8 Power Consumption 341.9 Summary and a Look Ahead 35Exercises 37Interview Questions . 52Chapter 2 Combinational Logic Design 552.1 Introduction 552.2 BooleanEquations 582.2.1 Terminology 582.2.2 Sum-of-Products Form . 582.2.3 Product-of-Sums Form . 602.3 BooleanAlgebra 602.3.1 Axioms . 612.3.2 Theorems of One Variable . 612.3.3 Theorems of Several Variables 622.3.4 The Truth Behind It All 642.3.5 Simplifying Equations 652.4 From Logic to Gates 662.5 Multilevel Combinational Logic 692.5.1 Hardware Reduction . 702.5.2 Bubble Pushing 712.6 X’s and Z’s, Oh My 732.6.1 Illegal Value: X . 732.6.2 Floating Value: Z 742.7 Karnaugh Maps 752.7.1 Circular Thinking . 762.7.2 Logic Minimization with K-Maps . 772.7.3 Don't Cares . 812.7.4 The Big Picture 822.8 Combinational Building Blocks 832.8.1 Multiplexers . 832.8.2 Decoders . 862.9 Timing. 882.9.1 Propagation and Contamination Delay 882.9.2 Glitches . 922.10 Summary 95Exercises 97Interview Questions 106Chapter 3 Sequential Logic Design 1093.1 Introduction. 1093.2 Latches and Flip-Flops . 1093.2.1 SR Latch . 1113.2.2 D Latch 1133.2.3 D FIip-Flop . 1143.2.4 Register . 1143.2.5 Enabled Flip-Flop . 1153.2.6 Resettable Flip-Flop 1163.2.7 Transistor-Level Latch and Flip-Flop Designs 1163.2.8 Putting It All Together . 1183.3 Synchronous Logic Design 1193.3.1 Some Problematic Circuits 1193.3.2 Synchronous Sequential Circuits 1203.3.3 Synchronous and Asynchronous Circuits . 1223.4 Finite State Machines 1233.4.1 FSM Design Example 1233.4.2 State Encodings . 1293.4.3 Moore and Mealy Machines 1323.4.4 Factoring State Machines . 1343.4.5 Deriving an FSM from a Schematic . 1373.4.6 FSM Review 1403.5 Timing of Sequential Logic . 1413.5.1 The Dynamic Discipline 1423.5.2 System Timing 1423.5.3 Clock Skew . 1483.5.4 Metastability 1513.5.5 Synchronizers . 1523.5.6 Derivation of Resolution Time 1543.6 Parallelism 1573.7 Summary . 161Exercises 162Interview Questions 171Chapter 4 Hardware Description Languages 1734.1 Introduction. 1734.1.1 Modules 1734.1.2 Language Origins . 1744.1.3 Simulation and Synthesis . 1754.2 Combinational Logic. 1774.2.1 Bitwise Operators . 1774.2.2 Comments and White Space 1804.2.3 Reduction Operators . 1804.2.4 Conditional Assignment 1814.2.5 Internal Variables . 1824.2.6 Precedence 1844.2.7 Numbers 1854.2.8 Z’s and X’s . 1864.2.9 Bit Swizzling 1884.2.10 Delays 1884.3 Structural Modeling 1904.4 Sequential Logic . 1934.4.1 Registers 1934.4.2 Resettable Registers 1944.4.3 Enabled Registers 1964.4.4 Multiple Registers . 1974.4.5 Latches . 1984.5 MoreCombinationalLogic. 1984.5.1 Case Statements . 2014.5.2 If Statements 2024.5.3 Truth Tables with Don’t Cares . 2054.5.4 Blocking and Nonblocking Assi